View SY89874U_746586.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

2.5GHz ANY DIFF. IN-TO-LVPECL Precision EdgeTM SY89874U PROGRAMMABLE CLOCK DIVIDER/FANOUT FINAL BUFFER WITH INTERNAL TERMINATION
FEATURES
I Integrated programmable clock divider and 1:2 fanout buffer I Guaranteed AC performance over temperature and voltage: * > 2.5GHz fMAX * < 250ps tr/tf * < 15ps within device skew I Low jitter design: * < 10ps (pk-pk) total jitter * < 1ps (rms) cycle-to-cycle jitter I Unique input termination and VT pin for DC-coupled and AC-coupled Inputs; CML, PECL, LVDS and HSTL I TTL/CMOS inputs for select and reset I 100k EP compatible LVPECL outputs I Parallel programming capability I Programmable divider ratios of 1, 2, 4, 8 and 16 I Low voltage operation 2.5V or 3.3V I Output disable function I -40C to 85C temperature range I Available in 16-pin (3mm x 3mm) MLFTM package Precision EdgeTM
DESCRIPTION
This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider ratio to create a frequencylocked, lower speed version of the input clock. Available divider ratios are 2, 4, 8 and 16, or straight pass-through. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz or 38MHz auxiliary clock components. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications. The /RESET input asynchronously resets the divider. In the pass-through function (divide by 1) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /N).
APPLICATIONS
I SONET/SDH line cards I Transponders I High-end, multiprocessor sensors
TYPICAL PERFORMANCE
OC-12 to OC-3 Translator/Divider
FUNCTIONAL BLOCK DIAGRAM
S2
LVDS 622MHz Clock In
Divide-by-4
LVPECL 155.5MHz Clock Out
/RESET Enable FF Enable MUX MUX
Q0 /Q0
622MHz In
IN
IN R0 VT R1 /IN S0 Decoder S1 Divided by 2, 4, 8 or 16
Q1 /Q1
/IN Q0
155.5MHz Out
VREF-AC
Precision Edge is a trademark of Micrel, Inc. MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc.
/Q0
Rev.: B
Amendment: /1
1
Issue Date: February 2003
Micrel
Precision EdgeTM SY89874U
PACKAGE/ORDERING INFORMATION
S0 S1 VCC GND
Ordering Information
IN VT VREF-AC /IN
Part Number SY89874UMI SY89874UMITR*
*Tape and Reel
16 15 14 13 Q0 /Q0 Q1 /Q1 1 2 3 4 5678 12 11 10 9
Package Type MLF-16 MLF-16
Operating Range Industrial Industrial
Package Marking 874U 874U
16-Pin MLFTM (MLF-16)
PIN DESCRIPTION
Pin Number 12, 9 1, 2, 3, 4 16, 15, 5 6 8 Pin Name IN, /IN Q0, /Q0 Q1, /Q1 S0, S1, S2 NC /RESET /DISABLE Pin Function Differential Input: Internal 50 termination resistors to VT input. Flexible input accepts any differential input. See "Input Interface Applications" section. Differential Buffered LVPECL Outputs: Divided by 1, 2, 4, 8 or 16. See "Truth Table." Unused PECL outputs may be left floating with no impact on jitter performance. Select Pins: See "Truth Table." LVTTL/CMOS logic levels. Internal 25k pull-up resistor. Logic HIGH if left unconnected (divided by 16 mode.) Input threshold is VCC/2. No Connect. LVTTL/CMOS Logic Levels: Internal 25k pull-up resistor. Logic HIGH if left unconnected. Apply LOW to reset the divider (divided by 2, 4, 8 or 16 mode). Also acts as a synchronous disable/enable function. The reset and disable function occurs on the next high-to-low clock input transition. Input threshold is VCC/2. Reference Voltage: Equal to VCC-1.4V (approx.). Used for AC-coupled applications only. Decouple the VREF-AC pin with a 0.01F capacitor. See "Input Interface Applications" section. Termination Center-Tap: For CML or LVDS inputs, leave this pin floating. Otherwise, see Figures 2a to 2f "Input Interface Applications" section. Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitor. Ground.
10 11 7, 14 13
VREF-AC VT VCC GND
TRUTH TABLE
/RESET(1) 1 1 1 1 1 0(1)
Note 1.
S2 0 1 1 1 1 1
S1 X 0 0 1 1 X
Reset/Disable function is asserted on the next clock input (IN, /IN) high-to-low transition.
S2 NC VCC /RESET
S0 X 0 1 0 1 X Outputs Reference Clock (pass through) Reference Clock /2 Reference Clock /4 Reference Clock /8 Reference Clock /16 Q = LOW, /Q = HIGH Clock Disable
2
Micrel
Precision EdgeTM SY89874U
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) .................................. -0.5V to +4.0V Input Voltage (VIN) .................................. -0.5V to VCC+0.3 ECL Output Current (IOUT) Continuous ......................................................... 50mA Surge ................................................................ 100mA Input Current IN, /IN (IIN) .......................................... 50mA VT Current (IVT) ...................................................... 100mA VREF-AC Sink/Source Current (IVREF-AC), Note 3 ....... 2mA Lead Temperature (soldering 10 sec.) ...................... 220C Storage Temperature (TS) ....................... -65C to +150C
Note 1.
Operating Ratings(Note 2)
Supply Voltage (VCC) ................+3.3V 10% or +2.5V 5% Ambient Temperature (TA) ......................... -40C to +85C Package Thermal Resistance MLFTM (JA) Still-Air ............................................................. 60C/W 500lfpm ............................................................ 54C/W MLFTM (JB), Note 4 Junction-to-Board ............................................ 32C/W
Note 2. Note 3. Note 4.
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. Due to the limited drive capability use for input of the same package only. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB.
DC ELECTRICAL CHARACTERISTICS(Notes 1, 2)
TA= -40C to +85C; Unless otherwise stated. Symbol VCC ICC RIN VIH VIL VIN VDIFF_IN |IIN| VREF-AC
Note 1. Note 2. Note 3. Note 4. Note 5. Note 6.
Parameter Power Supply Power Supply Current Differential Input Resistance (IN, /IN) Input High Voltage (IN, /IN) Input Low Voltage (IN, /IN) Input Voltage Swing Differential Input Voltage Swing Input Current (IN, /IN) Reference Voltage
Condition
Min 2.375
Typ
Max 3.63
Units V mA V V V V
No load, max. VCC 80 Note 3 Note 3 Notes 3, 4 Notes 3, 4, 5 Note 3 Note 6 0.1 -0.3 0.1 0.2 -
50 100 - - - - -
75 120 VCC+0.3 VCC+0.2 3.6
45
mA V
VCC-1.525 VCC-1.425 VCC-1.325
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Specification for packaged product only. Due to the internal termination (see "Input Structures" ) the input current depends on the applied voltages at IN, /IN and VT inputs. Do not apply a combination of voltages that causes the input current to exceed the maximum limit! See "Timing Diagram" for VIN definition. VIN (Max) is specified when VT is floating. See "Typical Operating Characteristics" section for VDIFF definition. Operating using VIN is limited to AC-coupled PECL or CML applications only. Connect directly to VT pin.
(100KEP) LVPECL DC ELECTRICAL CHARACTERISTICS(Notes 1, 2)
VCC = 3.3V 10% or 2.5V 5%; TA = -40C to +85C, RL = 50 to VCC -2V; Unless otherwise stated. Symbol VOH VOL VOUT VDIFF_OUT
Note 1. Note 2.
Parameter Output High Voltage Output Low Voltage Output Voltage Swing Differential Output Voltage Swing
Condition
Min
Typ
Max
Units V V mV V
VCC-1.145 VCC-1.020 VCC-0.895 VCC-1.945 VCC-1.820 VCC-1.695 550 1.10 800 1.60 1050 2.10
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Specification for packaged product only.
3
Micrel
Precision EdgeTM SY89874U
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS(Notes 1, 2)
VCC = 3.3V 10% or 2.5V 5%; TA = -40C to +85C; Unless otherwise stated. Symbol VIH VIL IIH IIL
Note 1. Note 2.
Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current
Condition
Min 2.0
Typ
Max
Units V
0.8 -125 20 -300
V A A
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Specification for packaged product only.
4
Micrel
Precision EdgeTM SY89874U
AC ELECTRICAL CHARACTERISTICS(Notes 1, 2)
VCC = 3.3V 10% or 2.5V 5%; TA = -40C to +85C; Unless otherwise stated. Symbol fMAX tPLH tPHL tSKEW Parameter Maximum Output Toggle Frequency Maximum Input Frequency Differential Propagation Delay IN to Q Within-Device Skew (diff.) Q0-Q1 Part-to-Part Skew (diff.) tRR Tjitter tr,tf
Note 1. Note 2. Note 3. Note 4. Note 5. Note 6.
Condition Output Swing 400mV Divide by 2, 4, 8, 16 Input Swing < 400mV Input Swing 400mV Note 3 Note 3 Note 4 Note 5 Note 6
Min 2.5 3.2 540 480
Typ
Max
Units GHz GHz
650 600 7
790 730 15 250
ps ps ps ps ps
Reset Recovery Time Cycle-to-Cycle Jitter Total Jitter Rise/Fall Time (20% to 80%)
600 1 10 70 150 250
ps(rms) ps(pk-pk) ps
Measured with 400mV input signal, 50% duty cycle, all outputs loaded with 50 to VCC-2V, unless otherwise stated. Specification for packaged product only. Skew is measured between outputs under identical transitions. See "Timing Diagram." Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. Tjitter_cc=Tn-Tn+1, where T is the time between rising edges of the output signal. Total jitter definition: with an ideal clock input, of frequency fMAX (device), no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value.
TIMING DIAGRAM
/RESET
VCC/2 tRR
IN VIN /IN VIN Swing /Q VOUT Swing Q tPD
5
Micrel
Precision EdgeTM SY89874U
TYPICAL OPERATING CHARACTERISTICS
VCC = 3.3V, VIN = 400mV, TA = 25C, unless otherwise stated.
QA Output Amplitude vs. Frequency
900 PROPAGATION DELAY (ps) 800 QA AMPLITUDE (mV) 700 600 500 400 300 200 100 1000 1500 2000 2500 3000 3500 0 0 500 900 800 700 600 500 400 300 200 100 0 0
IN to Q Propagation Delay vs. Input Swing
800 PROPAGATION DELAY (ps)
IN to Q Propagation Delay vs. Temperature
700
600
500
200 400 600 800 1000 1200 INPUT SWING (mV)
400 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C)
FREQUENCY (MHz)
622MHz Output
1.25GHz Output
/Q
Output Swing (100mV/div.)
Output Swing (100mV/div.)
Q TIME (200ps/div.)
/Q
Q
TIME (200ps/div.)
2.5GHz Output
/Q
Output Swing (100mV/div.)
Q
TIME (100ps/div.)
6
Micrel
Precision EdgeTM SY89874U
DEFINITION OF SINGLE-ENDED AND DIFFERENTIAL SWING
VIN, VOUT 800mV (typical)
VDIFF_IN, VDIFF_OUT 1600mV (typical)
Figure 1a. Single-Ended Swing
Figure 1b. Differential Swing
INPUT BUFFER STRUCTURE
VCC
VCC
1.86k
1.86k
25k S0 S1 S2 /RESET
R
1.86k IN 50 VT 50 /IN GND
1.86k
R
GND
Figure 2a. Simplified Differential Input Buffer
Figure 2b. Simplified TTL/CMOS Input Buffer
7
Micrel
Precision EdgeTM SY89874U
INPUT INTERFACE APPLICATIONS
VCC
VCC
VCC
VCC
VCC
VCC
IN CML /IN SY89874U GND NC NC VT VREF-AC 0.01F GND VCC CML
IN
PECL
IN /IN SY89874U
/IN SY89874U VT VREF-AC
GND .01F VCC-2V*
VT 50 NC VREF-AC
* Bypass with 0.01F to GND
Figure 3a. DC-Coupled CML Input Interface
Figure 3b. AC-Coupled CML Input Interface
Figure 3c. DC-Coupled PECL Input Interface
VCC
VCC
VCC
IN PECL /IN Rpd* Rpd* VCC GND GND 0.01F VT VREF-AC SY89874U
VCC
VCC
VCC
IN LVDS /IN SY89874U GND
IN HSTL /IN SY89874U GND VT NC GND VREF-AC
NC NC
VT VREF-AC
*Note. 3.3V = Rpd = 100 2.5V = Rpd = 50
Figure 3d. AC-Coupled PECL Input Interface
Figure 3e. LVDS Input Interface
Figure 3f. HSTL Input Interface
RELATED PRODUCT AND SUPPORT DOCUMENTATION
Part Number SY89871U Function 2.5GHz Any Diff. In-to-LVPECL Programmable Clock Divider/Fanout Buffer w/Internal Termination MLFTM Application Note HBW Solutions New Products and Applications Data Sheet Link http://www.micrel.com/product-info/products/sy89871u.shtml
http://www.amkor.com/products/notes_papers/mlf_appnote_0902.pdf http://www.micrel.com/product-info/products/solutions.shtml
8
Micrel
Precision EdgeTM SY89874U
LVPECL OUTPUT TERMINATION RECOMMENDATIONS
+3.3V
+3.3V
ZO = 50 ZO = 50
R1 130
R1 130
+3.3V
R2 82
R2 82
Vt = VCC --2V
Figure 4a. Parallel Termination-Thevenin Equivalent
Note 1. For +2.5V systems: R1 = 250, R2 = 62.5
+3.3V
Z = 50 Z = 50 50 50 Rb
+3.3V
"source" 50
"destination" (Optional) C1 0.01F
Figure 4b. Three-Resistor "Y-Termination"
Note 1. Note 2. Note 3. Note 4. Power-saving alternative to Thevenin termination. Place termination resistors as close to destination inputs as possible. Rb resistor sets the DC bias voltage, equal to Vt. For +3.3V systems Rb = 46 to 50. For +2.5V systems Rb = 39 C1 is an optional bypass capacitor intended to compensate for any tr/tf mismatches.
+3.3V R1 130 ZO = 50 /Q Vt = VCC --2V R2 82
+3.3V R1 130 Vt = VCC --1.3V R3 +3.3V 1k
+3.3V
Q
R4 1.6k R2 82
Figure 4d. Terminating Unused I/O
Note 1. Note 2. Unused output (/Q) must be terminated to balance the output. For +2.5V systems: R1 = 250, R2 = 62.5, R3 = 1.25k, R4 = 1.2k.
9
Micrel
Precision EdgeTM SY89874U
16 LEAD MicroLeadFrameTM (MLF-16)
0.42 +0.18 -0.18 0.23 +0.07 -0.05 0.01 +0.04 -0.01 0.65 +0.15 -0.65 0.20 REF. 0.42
+0.18 -0.18
0.85 +0.15 -0.65 3.00BSC 2.75BSC
16 1
1.60 +0.10 -0.10 PIN 1 ID
N 1
0.50 DIA
2 3 4
2.75BSC 3.00BSC
2 3 4
1.60 +0.10 -0.10
12 max SEATING PLANE TOP VIEW CC C L 4 0.23 +0.07 -0.05 0.01 +0.04 -0.01 1. 2. 3. 4.
0.42 +0.18 -0.18
0.5 BSC 1.5 REF BOTTOM VIEW
0.40 +0.05 -0.05
0.5BSC FOR EVEN TERMINAL/SIDE
SECTION "C-C" SCALE: NONE
DIMENSIONS ARE IN mm. DIE THICKNESS ALLOWABLE IS 0.305mm MAX. PACKAGE WARPAGE MAX 0.05mm. THIS DIMENSION APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.20mm AND 0.25mm FROM TIP. 5. APPLIES ONLY FOR TERMINALS
Rev. 02
Package EP- Exposed Pad
Die
CompSide Island
Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane
PCB Thermal Consideration for 16-Pin MLFTM Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes: Note 1. Package meets Level 2 moisture sensitivity classification, and is shipped in dry-pack form. Note 2. Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC.
TEL
1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA
FAX
+ 1 (408) 944-0800
+ 1 (408) 944-0970
WEB
http://www.micrel.com
The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2003 Micrel, Incorporated.
10

▲Up To Search▲

Price & Availability of SY89874U

	To Download SY89874U Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .